The present application relates generally to the manufacture of semiconductor devices, and more specifically to a process for manufacturing self-aligned contacts.
Metal-oxide-semiconductor (MOS) transistors, such as MOS field effect transistors (MOSFETs), are used in the manufacture of integrated circuits. MOS transistors typically include gate dielectric and gate conductor layers, spacers, and diffusion regions such as source/drain regions. An interlayer dielectric (ILD) is commonly formed over the transistor structures and covers the diffusion regions.
Separate electrical connections are made to the gate, source, and drain using contact plugs that are typically formed of a metal such as tungsten. The contact plugs are commonly fabricated by initially patterning the ILD layer to form vias. Metal is deposited into the vias to form the contact plugs.
With advanced process nodes, manufacturing windows demand precise critical dimension (CD) control and alignment precision. Misaligned conductive elements, for example, can create short circuits, such as a contact-to-gate short, which adversely affect yield and performance.
Self-aligned contact processes can be used to control feature registration and critical dimension (CD). In various processes, a nitride capping layer is inlaid over gate contacts and a polishing step is used to remove the overburden and expose adjacent trench locations used to form source/drain contacts. As will be appreciated, however, the absence of an etch-selective stopping layer may result in under- or over-polishing of the nitride capping layer.
A comparative, post-replacement metal gate (RMG) architecture is shown in FIG. 1. Gate structures 20, which include a gate dielectric layer 21, work function metal 22 and fill metal 24, are formed over a semiconductor fin 12, and are laterally spaced from source drain regions 14 and interlayer dielectric 40 by sidewall spacer layers 30. After forming nitride capping layer 60, and referring also to FIG. 2, a polishing step is used to remove excess nitride 60 and expose the ILD oxide 40.
Due to poor etch selectivity between the nitride capping layer 60 and the ILD oxide 40, however, it is challenging to control the final (polished) thickness of the nitride capping layer 60. Both under-polishing and over-polishing can create undesired results. In an under-polished condition, for instance, nitride material remaining over the ILD oxide 40 may block etching of the ILD oxide during a subsequent etching step, resulting in an incomplete or absent source/drain contact and an electrical open. Over-polishing of the nitride capping layer 60, on the other hand, may result in insufficient nitride material over the gate structure 20, resulting in an electrical short between gate and source/drain contacts.